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? semiconductor components industries, llc, 2005 september, 2005 ? rev. 15 1 publication order number: CS8151/d CS8151 5.0 v, 100 ma low dropout linear regulator with watchdog, reset , and wake up the CS8151 is a precision 5.0 v, 100 ma micro?power voltage regulator with very low quiescent current (400 a typical at 200 a load). the 5.0 v output is accurate within 2% and supplies 100 ma of load current with a typical dropout voltage of 400 mv. microprocessor control logic includes watchdog, wake up and reset . this unique combination of low quiescent current and full microprocessor control makes the CS8151 ideal for use in battery operated, microprocessor controlled equipment. the CS8151 wake up function brings the microprocessor out of sleep mode. the microprocessor in turn, signals its wake up status back to the CS8151 by issuing a watchdog signal. the watchdog logic function monitors an input signal (wdi) from the microprocessor. the CS8151 responds to the falling edge of the watchdog signal which it expects at least once during each wake?up period. when the correct watchdog signal is received, a falling edge is issued on the wake?up signal line. reset is independent of v in and operates correctly to an output voltage as low as 1.0 v. a reset signal is issued in any of three situations. during power up the reset is held low until the output voltage is in regulation. during operation if the output voltage shifts below the regulation limits, the reset toggles low and remains low until proper output voltage regulation is restored. and finally, a reset signal is issued if the regulator does not receive a watchdog signal within the wake up period. the reset pulse width, wake up signal frequency, and wake up delay time are all set by one external capacitor c delay . the regulator is protected against short circuit, over voltage, and thermal runaway conditions. the device can withstand 74 v peak transients, making it suitable for use in automotive environments. features ? 5.0 v 2%/100 ma output voltage ? micropower compatible control functions ? wake up ? watchdog ? reset ? low dropout voltage: 400 mv @ 100 ma ? low sleep mode quiescent current (400 a typ) ? protection features ? thermal shutdown ? short circuit ? 74 v peak transient capability ? reverse transient (?50 v) ? internally fused leads in pdip?16 and so?16l packages ? pb?free packages are available so?16l dwf suffix case 751g 1 16 to?220?7 t suffix case 821e 1 7 to?220?7 tva suffix case 821j 1 d 2 pak?7 dps suffix case 936ab 1 7 pdip?16 nf suffix case 648 1 16 see general marking information in the device marking section on page 10 of this data sheet. device marking information http://onsemi.com to?220?7 tha suffix case 821h 1 7 see detailed ordering and shipping information in the package dimensions section on page 11 of this data sheet. ordering information pdip?8 n suffix case 626 1 8
CS8151 http://onsemi.com 2 pin connections v in v out nc sense wdi gnd gnd gnd gnd gnd wake up nc reset nc delay nc 1 d 2 pak 7?pin to?220 seven lead 1 16 1 v in v out nc sense wdi nc gnd gnd gnd gnd wake up nc reset nc delay nc 16 1 tab = gnd pin 1. v out 2. v in 3. wdi 4. gnd 5. wake up 6. reset 7. delay pdip?16 so?16l 1 8 v out gnd nc delay v in wdi wake up reset pdip?8 figure 1. block diagram v in delay wdi reset v out wake u p sense gnd overvoltage shutdown current source (circuit bias) current limit sense wake up circuit +? timing circuit watchdog circuit thermal shutdown falling edge detector bandgap reference reset circuit error amplifier v out v out internally connected on to?220 and d 2 pak
CS8151 http://onsemi.com 3 maximum ratings* rating value unit power dissipation internally limited ? output current (v out , reset , wake up) internally limited ? reverse battery ?15 v peak transient voltage (60 v load dump @ v in = 14 v) +74 v maximum negative transient (t < 2.0 ms) ?50 v esd susceptibility (human body model) 2.0 kv esd susceptibility (machine model) 200 v logic inputs/outputs ?0.3 to +6.0 v storage temperature range ?55 to +150 c lead temperature soldering wave solder (through hole styles only) (note 1) reflow (smd styles only) (notes 2 & 3) 260 peak 240 peak c c maximum ratings are those values beyond which device damage can occur. maximum ratings applied to the device are individual str ess limit values (not normal operating conditions) and are not valid simultaneously. if these limits are exceeded, device functional operation i s not implied, damage may occur and reliability may be affected. 1. 10 seconds max 2. 60 seconds max above 183 c 3. ?5 c / +0 c allowable conditions *the maximum package power dissipation must be observed electrical characteristics (?40 c t a 125 c, ?40 c t j 150 c, 6.0 v v in 26 v, 100 a i out 100 ma, c 2 = 47 f (esr < 8.0 ), c delay = 0.1 f; unless otherwise specified.) characteristic test conditions min typ max unit output section output voltage, v out 9.0 v < v in < 16 v 6.0 v < v in < 26 v, 0 < i out < 100 ma 4.90 4.85 5.0 5.0 5.10 5.15 v v dropout voltage (v in ? v out ) i out = 100 ma i out = 100 a ? ? 400 100 600 150 mv mv load regulation v in = 14 v, 100 a < i out < 100 ma ? 10 50 mv line regulation i out = 1.0 ma, 6.0 v < v in < 26 v ? 10 50 mv ripple rejection 7.0 v < v in < 17 v @ f = 120 hz, i out = 100 ma 60 75 ? db current limit v out = 4.5 v 100 250 ? ma thermal shutdown ? 150 180 210 c overvoltage shutdown v out < 1.0 v 50 56 62 v quiescent current i out = 200 a (sleep) i out = 50 ma i out = 100 ma (wake up) ? ? ? 0.4 4.0 12 0.75 ? 20 ma ma ma reverse current v out = 5.0 v, v in = 0 v ? 1.0 1.5 ma reset threshold high (rth) rth v out increasing v out ? 0.3 ? v out ? 0.04 v threshold low (rtl) rtl v out decreasing 4.5 4.7 4.91 v hysteresis rth ? rtl 150 200 250 mv output low 1.0 v < v out rtl, i out = 25 a ? 0.2 0.8 v output high i out = 25 a, v out > rth 3.8 4.2 5.1 v current limit reset = 0 v, v out > v rth (sourcing) reset = 5.0 v, v out > 1.0 v (sinking) 0.025 0.1 0.5 12 1.30 80 ma ma delay time por mode 3.0 5.0 7.0 ms
CS8151 http://onsemi.com 4 electrical characteristics (?40 c t a 125 c, ?40 c t j 150 c, 6.0 v v in 26 v, 100 a i out 100 ma, c 2 = 47 f (esr < 8.0 ), c delay = 0.1 f; unless otherwise specified.) characteristic unit max typ min test conditions watchdog input threshold high ? ? 1.4 2.0 v threshold low ? 0.8 1.3 ? v hysteresis ? 25 100 ? mv input current 0 < wdi < 6.0 v ?10 0 +10 a pulse width 50% wdi falling edge to 50% wdi rising edge and 50% wdi rising edge to 50% wdi falling edge (see figures 2, 3, and 4) 5.0 ? ? s wake up output wake up period see figure 2 30 40 50 ms wake up duty cycle nominal see figure 4 40 50 60 % reset high to wake up rising delay time 50% reset rising edge to 50% wake up edge (see figures 2, 3, and 4) 15 20 25 ms wake up response to watchdog input 50% wdi falling edge to 50% wake up falling edge ? 2.0 10 s wake up response to reset 50% reset falling edge to 50% wake up falling edge, v out = 5.0 v 4.5 v ? 2.0 10 s output low i out = 25 a (sinking) ? 0.2 0.8 v output high i out = 25 a (sourcing) 3.8 4.2 5.1 v current limit wake up = 5.0 v wake up = 0 v 0.025 0.05 1.0 ? 7.0 3.5 ma ma
CS8151 http://onsemi.com 5 package pin description package pin # to?220 & d 2 pak dip?16 so?16l pin symbol function 1 8 8 v out regulated output voltage 5.0 v 2%. 2 9 9 v in supply voltage to the ic. 3 11 11 wdi cmos/ttl compatible input lead. the watchdog function monitors the falling edge of the incoming signal. 4 4, 5, 12, 13 4, 5, 6, 12, 13* gnd ground connection. 5 14 14 wake up cmos/ttl compatible output consisting of a continuously generated signal used to wake up the microprocessor from sleep mode. 6 15 15 reset cmos/ttl compatible output lead reset goes low whenever v out drops by more than 6.0% from nominal, or during the absence of a correct watchdog signal. 7 16 16 delay input lead from timing capacitor for reset and wake up signal. ? 7 7 sense kelvin connection which allows remote sensing of the output voltage for improved regulation. if remote sensing is not required, connect to v out . *pin 6 gnd is not directly shorted to the fused paddle gnd. the fused paddle gnd (pins 4, 5, 12, 13) is connected through the s ubstrate. pin 6 must be electrically connected to at least one of the fused paddle gnd?s on the pc board. package pin description package pin # pdip?8 pin symbol function 1 v in supply voltage to the ic. 2 wdi cmos/ttl compatible input lead. the watchdog function monitors the falling edge of the incoming signal. 3 wake up cmos/ttl compatible output consisting of a continuously generated signal used to wake up the microprocessor from sleep mode. 4 reset cmos/ttl compatible output lead reset goes low whenever v out drops by more than 6.0% from nominal, or during the absence of a correct watchdog signal. 5 delay input lead from timing capacitor for reset and wake up signal. 6 nc no connection. 7 gnd ground connection. 8 v out regulated output voltage 5.0 v 2%.
CS8151 http://onsemi.com 6 timing diagrams watchdog pulse width v in reset wake up wdi v out wake up duty cycle = 50% power up sleep mode normal operation with varying watchdog signal reset high to wake up delay time por figure 2. power up, sleep mode and normal operation figure 3. error condition: watchdog remains low and a reset is issued v in reset wake up wdi v out por reset high to wake up delay time reset delay time reset high to wake up delay time wake up period por reset wake up wdi v out watchdog pulse width rtl por power down wake up period figure 4. power down and restart sequence
CS8151 http://onsemi.com 7 definition of terms dropout voltage: the input?output voltage differential at which the circuit ceases to regulate against further reduction in input voltage. measured when the output voltage has dropped 100mv from the nominal value obtained at 14v input, dropout voltage is dependent upon load current and junction temperature. input voltage: the dc voltage applied to the input terminals with respect to ground. line regulation: the change in output voltage for a change in the input voltage. the measurement is made under conditions of low dissipation or by using pulse techniques such that the average chip temperature is not significantly affected. load regulation: the change in output voltage for a change in load current at constant chip temperature. quiescent curr ent: the part of the positive input current that does not contribute to the positive load current. the regulator ground lead current. ripple rejection: the ratio of the peak?to?peak input ripple voltage to the peak?to?peak output ripple voltage. current limit: peak current that can be delivered to the output. circuit description functional description to reduce the drain on the battery a system can go into a low current consumption mode when ever its not performing a main routine. the wake up signal is generated continuously and is used to interrupt a microcontroller that is in sleep mode. the nominal output is a 5.0 v square wave with a duty cycle of 50% at a frequency that is determined by a timing capacitor, c delay . when the microprocessor receives a rising edge from the wake up output, it must issue a watchdog pulse and check its inputs to decide if it should resume normal operations or remain in the sleep mode. figure 5. wake up response to wdi wake up response to wdi wake up wdi figure 6. wake up response to reset (low voltage) wake up response to reset reset wake up the first falling edge of the watchdog signal causes the wake up to go low within 2.0 s (typ) and remain low until the next wake up cycle (see figure 5). other watchdog pulses received within the same cycle are ignored (figures 2, 3, and 4). during power up, reset is held low until the output voltage is in regulation. during operation, if the output voltage shifts below the regulation limits, the reset toggles low and remains low until proper output voltage regulation is restored. after the reset delay, reset returns high. the watchdog circuitry continuously monitors the input watchdog signal (wdi) from the microprocessor. the absence of a falling edge on the w atchdog input during one wake up cycle will cause a reset pulse to occur at the end of the wake up cycle (see figure 3). the wake up output is pulled low during a reset regardless of the cause of the reset . after the reset returns high, the wake up cycle begins again (see figure 3). the reset pulse width, wake up signal frequency and reset high to wake up delay time are all set by one external capacitor c delay . wake up period = (4 10 5 )c delay reset delay time = (5 10 4 )c delay reset high to wake up delay time = (2 10 5 )c delay capacitor temperature coef ficient and tolerance as well as the tolerance of the CS8151 must be taken into account in order to get the correct system tolerance for each parameter.
CS8151 http://onsemi.com 8 application notes output stage protection the output stage is protected against overvoltage, short circuit and thermal runaway conditions (see figure 7). if the input voltage rises above the overvoltage shutdown threshold (e.g. load dump), the output shuts down. this response protects the internal circuitry and enables the ic to survive unexpected voltage transients. should the junction temperature of the power device exceed 180 c (typ) the power transistor is turned off. thermal shutdown is an effective means to prevent die overheating since the power transistor is the principle heat source in the ic. figure 7. typical circuit waveforms for output stage protection v in v out i out > 50 v load dump short circuit thermal shutdown stability considerations the output or compensation capacitor c2 (see figure 8) helps determine three main characteristics of a linear regulator: startup delay, load transient response and loop stability. figure 8. test and application circuit showing output compensation CS8151 v in c1* 0.1 f v out reset c2** 10 f *c1 required if regulator is located far from the power supply filter. **c2 required for stability. r rst the capacitor value and type should be based on cost, availability, size and temperature constraints. a tantalum or aluminum electrolytic capacitor is best, since a film or ceramic capacitor with almost zero esr can cause instability. the aluminum electrolytic capacitor is the least expensive solution, but, if the circuit operates at low temperatures (?25 c to ?40 c), both the value and esr of the capacitor will vary considerably. the capacitor manufacturers data sheet usually provide this information. the value for the output capacitor c2 shown in the test and applications circuit should work for most applications, however it is not necessarily the optimized solution. to determine an acceptable value for c2 for a particular application, start with a tantalum capacitor of the recommended value and work towards a less expensive alternative part. step 1: place the completed circuit with a tantalum capacitor of the recommended value in an environmental chamber at the lowest specified operating temperature and monitor the outputs with an oscilloscope. a decade box connected in series with the capacitor will simulate the higher esr of an aluminum capacitor. leave the decade box outside the chamber, the small resistance added by the longer leads is negligible. step 2: with the input voltage at its maximum value, increase the load current slowly from zero to full load while observing the output for any oscillations. if no oscillations are observed, the capacitor is large enough to ensure a stable design under steady state conditions. step 3: increase the esr of the capacitor from zero using the decade box and vary the load current until oscillations appear. record the values of load current and esr that cause the greatest oscillation. this represents the worst case load conditions for the regulator at low temperature. step 4: maintain the worst case load conditions set in step 3 and vary the input voltage until the oscillations increase. this point represents the worst case input voltage conditions. step 5: if the capacitor is adequate, repeat steps 3 and 4 with the next smaller valued capacitor. a smaller capacitor will usually cost less and occupy less board space. if the output oscillates within the range of expected operating conditions, repeat steps 3 and 4 with the next lar ger standard capacitor value. step 6: test the load transient response by switching in various loads at several frequencies to simulate its real working environment. vary the esr to reduce ringing. step 7: raise the temperature to the highest specified operating temperature. vary the load current as instructed in step 5 to test for any oscillations. once the minimum capacitor value with the maximum esr is found, a safety factor should be added to allow for the tolerance of the capacitor and any variations in regulator performance. most good quality aluminum electrolytic capacitors have a tolerance of 20% so the minimum value found should be increased by at least 50% to allow for this tolerance plus the variation which will occur at low
CS8151 http://onsemi.com 9 temperatures. the esr of the capacitor should be less than 50% of the maximum allowable esr found in step 3 above. calculating power dissipation in a single output linear regulator the maximum power dissipation for a single output regulator (figure 9) is: p d(max) ( v in(max) v out(min) ) i out(max) v in(max) i q (1) where: v in(max) is the maximum input voltage, v out(min) is the minimum output voltage, i out(max) is the maximum output current for the application, and i q is the quiescent current the regulator consumes at i out(max) . once the value of p d(max) is known, the maximum permissible value of r ja can be calculated: r ja 150 c t a p d (2) the value of r ja can then be compared with those in the package section of the data sheet. those packages with r ja ?s less than the calculated value in equation 2 will keep the die temperature below 150 c. smart regulator ? i q control features i out i in figure 9. single output regulator with key performance parameters labeled v in v out } in some cases, none of the packages will be sufficient to dissipate the heat generated by the ic, and an external heatsink will be required. a heat sink effectively increases the surface area of the package to improve the flow of heat away from the ic and into the surrounding air. heat sinks each material in the heat flow path between the ic and the outside environment will have a thermal resistance. like series electrical resistances, these resistances are summed to determine the value of r ja : r ja r jc r cs r sa (3) where: r jc = the junction?to?case thermal resistance, r cs = the case?to?heatsink thermal resistance, and r sa = the heatsink?to?ambient thermal resistance. r jc appears in the package section of the data sheet. like r ja , it too is a function of package type. r cs and r sa are functions of the package type, heatsink and the interface between them. these values appear in heatsink data sheets of heatsink manufacturers. figure 10. application diagram v in c delay v out wdi reset gnd CS8151 microprocessor wake up c delay c1 c2 v cc i/o reset i/o battery
CS8151 http://onsemi.com 10 typical performance characteristics figure 11. CS8151 output stability with output capacitor change 1000 100 10 1 0.1 0.01 0 10 20304050 100 esr ( ) i out output current (ma) c vout = 47 f 60 70 80 90 unstable region stable region c vout = 1 f c vout = 10 f c vout = 47 f c vout = 1 f unstable region marking diagrams a = assembly location wl = wafer lot y, yy = year ww = work week g = pb?free package so?16l dwf suffix case 751g d 2 pak 7?pin dps suffix case 936ab to?220 seven lead t suffix case 821e cs 8151 awlywwg 1 to?220 seven lead tva suffix case 821j pdip?16 nf suffix case 648 to?220 seven lead tha suffix case 821h cs 8151 awlywwg 1 16 1 CS8151 awlyywwg 16 1 CS8151ynf16 awlyywwg cs 8151 awlywwg 1 cs 8151 awlywwg 1 pdip?8 n suffix case 626 CS8151c awl yywwg
CS8151 http://onsemi.com 11 ordering information device package shipping ? CS8151yt7 to?220?7 50 units / rail CS8151yt7g to?220?7 (pb?free) 50 units / rail CS8151ytva7 to?220?7 50 units / rail CS8151ytva7g to?220?7 (pb?free) 50 units / rail CS8151ytha7 to?220?7 50 units / rail CS8151ytha7g to?220?7 (pb?free) 50 units / rail CS8151ydps7 d 2 pak?7 50 units / rail CS8151ydps7g d 2 pak?7 (pb?free) 50 units / rail CS8151ydpsr7 d 2 pak?7 750 units / tape & reel CS8151ydpsr7g d 2 pak?7 (pb?free) 750 units / tape & reel CS8151cgn8 pdip?8 50 units / rail CS8151cgn8g pdip?8 (pb?free) 50 units / rail CS8151ynf16 pdip?16 25 units / rail CS8151ynf16g pdip?16 (pb?free) 25 units / rail CS8151ydwf16 so?16l 47 units / rail CS8151ydwf16g so?16l (pb?free) 47 units / rail CS8151ydwfr16 so?16l 1000 units / tape & reel CS8151ydwfr16g so?16l (pb?free) 1000 units / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
CS8151 http://onsemi.com 12 package dimensions to?220?7 t suffix case 821e?04 issue d dim a min max min max millimeters 0.600 0.610 15.24 15.49 inches b 0.386 0.403 9.80 10.23 c 0.170 0.180 4.32 4.56 d 0.028 0.037 0.71 0.94 g 0.045 0.055 1.15 1.39 h j 0.018 0.026 0.46 0.66 k 1.028 1.042 26.11 26.47 l 0.355 0.365 9.02 9.27 m 5 nom q 0.142 0.148 3.61 3.75 u 0.490 0.501 12.45 12.72 v 0.045 0.055 1.15 1.39 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension d does not include dambar protrusion. allowable protrusion shall be 0.003 (0.076) total in excess of the d dimension at maximum material condition. 4. 821e?01 thru 821?03 obsolete, new standard 821e?04. 5 nom 0.088 0.102 2.24 2.59 a k u l q d g b c m m v m j h seating plane optional chamfer 175 to?220?7 tva suffix case 821j?02 issue a notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension d does not include interconnect bar (dambar) protrusion. dimension d including protrusion shall not exceed 10.92 (0.043) maximum. a u d g b t m 0.356 (0.014) m q 7 pl ?q? k f j c e ?t? n l m w dim min max min max millimeters inches a 0.560 0.590 14.22 14.99 b 0.385 0.415 9.77 10.54 c 0.160 0.190 4.06 4.82 d 0.023 0.037 0.58 0.94 e 0.045 0.055 1.14 1.40 f 0.540 0.555 13.72 14.10 g 0.050 bsc 1.27 bsc j 0.014 0.022 0.36 0.56 k 0.785 0.800 19.94 20.32 l 0.322 0.337 8.18 8.56 m 0.073 0.088 1.85 2.24 n 0.090 0.115 2.28 2.91 q 0.146 0.156 3.70 3.95 s 0.164 0.179 4.17 4.55 u 0.460 0.475 11.68 12.07 w 33 r s h h 14.48 15.11 0.570 0.595 r 0.289 0.304 7.34 7.72
CS8151 http://onsemi.com 13 package dimensions to?220?7 tha suffix case 821h?02 issue a notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension d does not include interconnect bar (dambar) protrusion. dimension d including protrusion shall not exceed 10.92 (0.043) maximum. 1. leads maintain a right angle with respect to the package body to with 0.020". a u d g b t m 0.356 (0.014) m q 7 pl ?q? k f j c e ?t? n l m w s dim min max min max millimeters inches a 0.560 0.590 14.22 14.99 b 0.385 0.415 9.77 10.54 c 0.160 0.190 4.06 4.82 d 0.023 0.037 0.58 0.94 e 0.045 0.055 1.14 1.40 f 0.568 0.583 14.43 14.81 g 0.050 bsc 1.27 bsc j 0.015 0.022 0.38 0.56 k 0.728 0.743 18.49 18.87 l 0.322 0.337 8.18 8.56 m 0.101 0.116 2.57 2.95 n 0.090 0.115 2.28 2.91 q 0.146 0.156 3.70 3.95 s 0.150 0.200 3.81 5.08 u 0.460 0.475 11.68 12.07 w 33
CS8151 http://onsemi.com 14 package dimensions d 2 pak?7 (short lead) dps suffix case 936ab?01 issue a dim min max min max millimeters inches a 0.396 0.406 10.05 10.31 b 0.326 0.336 8.28 8.53 c 0.170 0.180 4.31 4.57 d 0.026 0.036 0.66 0.91 e 0.045 0.055 1.14 1.40 g 0.050 ref 1.27 ref h 0.539 0.579 13.69 14.71 k l 0.000 0.010 0.00 0.25 m 0.100 0.110 2.54 2.79 n 0.017 0.023 0.43 0.58 notes: 1. dimensions and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. a b k e p m n d g u v s h l c r 0.055 0.066 1.40 1.68 p 0.058 0.078 1.47 1.98 r s 0.095 0.105 2.41 2.67 u 0.256 ref 6.50 ref v 0.305 ref 7.75 ref 0 8 0 8 terminal 8 8.26 0.325 10.54 0.415 0.96 0.038 scale 3:1 mm inches 9.5 0.374 3.25 0.128 2.16 0.085 3.8 0.150 1.27 0.050 c l c l 1 *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint*
CS8151 http://onsemi.com 15 package dimensions pdip?8 n suffix case 626?05 issue l notes: 1. dimension l to center of lead when formed parallel. 2. package contour optional (round or square corners). 3. dimensioning and tolerancing per ansi y14.5m, 1982. 14 5 8 f note 2 ?a? ?b? ?t? seating plane h j g d k n c l m m a m 0.13 (0.005) b m t dim min max min max inches millimeters a 9.40 10.16 0.370 0.400 b 6.10 6.60 0.240 0.260 c 3.94 4.45 0.155 0.175 d 0.38 0.51 0.015 0.020 f 1.02 1.78 0.040 0.070 g 2.54 bsc 0.100 bsc h 0.76 1.27 0.030 0.050 j 0.20 0.30 0.008 0.012 k 2.92 3.43 0.115 0.135 l 7.62 bsc 0.300 bsc m ??? 10 ??? 10 n 0.76 1.01 0.030 0.040 package thermal data parameter dip?8 unit r jc typical 52 c/w r ja typical 100 c/w pdip?16 nf suffix case 648?08 issue t notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of leads when formed parallel. 4. dimension b does not include mold flash. 5. rounded corners optional. ?a? b f c s h g d j l m 16 pl seating 18 9 16 k plane ?t? m a m 0.25 (0.010) t dim min max min max millimeters inches a 0.740 0.770 18.80 19.55 b 0.250 0.270 6.35 6.85 c 0.145 0.175 3.69 4.44 d 0.015 0.021 0.39 0.53 f 0.040 0.70 1.02 1.77 g 0.100 bsc 2.54 bsc h 0.050 bsc 1.27 bsc j 0.008 0.015 0.21 0.38 k 0.110 0.130 2.80 3.30 l 0.295 0.305 7.50 7.74 m 0 10 0 10 s 0.020 0.040 0.51 1.01
CS8151 http://onsemi.com 16 package dimensions so?16l dwf suffix case 751g?03 issue c d 14x b 16x seating plane s a m 0.25 b s t 16 9 8 1 h x 45 m b m 0.25 h 8x e b a e t a1 a l c notes: 1. dimensions are in millimeters. 2. interpret dimensions and tolerances per asme y14.5m, 1994. 3. dimensions d and e do not inlcude mold protrusion. 4. maximum mold protrusion 0.15 per side. 5. dimension b does not include dambar protrusion. allowable dambar protrusion shall be 0.13 total in excess of the b dimension at maximum material condition. dim min max millimeters a 2.35 2.65 a1 0.10 0.25 b 0.35 0.49 c 0.23 0.32 d 10.15 10.45 e 7.40 7.60 e 1.27 bsc h 10.05 10.55 h 0.25 0.75 l 0.50 0.90 0 7 package thermal data parameter to?220?7 d 2 pak?7 dip?16 so?16l unit r jc typical 1.8 1.8 15 18 c/w r ja typical 50 10?50* 50 75 c/w *depending on thermal properties of substrate. r ja = r jc + r ca . on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800?282?9855 toll free usa/canada japan : on semiconductor, japan customer focus center 2?9?1 kamimeguro, meguro?ku, tokyo, japan 153?0051 phone : 81?3?5773?3850 CS8151/d smart regulator is a registered trademark of semiconductor components industries, llc (scillc). literature fulfillment : literature distribution center for on semiconductor p.o. box 61312, phoenix, arizona 85082?1312 usa phone : 480?829?7710 or 800?344?3860 toll free usa/canada fax : 480?829?7709 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : http://onsemi.com order literature : http://www.onsemi.com/litorder for additional information, please contact your local sales representative.

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